Today's computer systems are becoming increasingly sophisticated, permitting users to perform an ever increasing variety of computing tasks at faster and faster rates. The size of the memory and the speed at which it can be accessed bear heavily upon the overall speed of the computer system.
Memory for a computer system is technically any form of electronic, magnetic or optical storage; however it is generally divided up into different categories based in part upon speed and functionality. The two general categories of computer memory are main memory and mass storage. Main memory is generally comprised of fast, expensive volatile random access memory that is connected directly to the processor by a memory buss.
Mass storage devices are typically permanent non-volatile memory stores which are understood to be less expensive, slow, large capacity devices such as bard drives, tape drives, optical media, and other mass storage devices. The primary objective of mass storage devices is to store an application or data until it is required for execution in main memory. In contrast to the main memory stores that may operate with access times of less than 100 nanoseconds, these mass storage devices operate with access times generally in excess of 1 millisecond.
Generally, the principle underlying the storage of data in a magnetic media (main or mass storage) is the ability to change, and or reverse, the relative orientation of the magnetization of a storage data bit (i.e the logic state of a “0” or a “1”). The coercivity of a material is the level of demagnetizing force that must be applied to a magnetic particle to reduce and or reverse the magnetization of the particle. Generally speaking, the smaller the magnetic particle the higher it's coercivity.
A prior art magnetic memory cell may be a tunneling magnetoresistance memory cell (TMR), a giant magnetoresistance memory cell (GMR), or a colossal magnetoresistance memory cell (CMR), each of which generally includes a data layer (also called a storage layer or bit layer), a reference layer, and an intermediate layer between the data layer and the reference layer. The data layer, the reference layer, and the intermediate layer can be made from one or more layers of material.
The data layer is usually a layer of magnetic material that stores a bit of data as an orientation of magnetization that may be altered in response to the application of external magnetic fields. More specifically, the orientation of magnetization of the data layer representing the logic state can be rotated (switched) from a first orientation representing a logic state of “0” to a second orientation, representing a logic state of “1”, and/or vice versa. Generally speaking, the magnetic field used to accomplish the switch in orientation is known as a “coercive switching field,” or even more simply as a “switching field.”
The reference layer is usually a layer of magnetic material in which an orientation of magnetization is “pinned”, as in fixed, in a predetermined direction. Often several layers of magnetic material are required and function as one to effectuate a stable pinned reference layer. The predetermined direction is determined and established by microelectronic processing steps employed in the fabrication of the magnetic memory cell.
Typically, the logic state (a “0” or a “1”) of a magnetic memory cell depends on the relative orientations of magnetization in the data layer and the reference layer. For example, when an electrical potential bias is applied across the data layer and the reference layer in a TMR cell (also known as a tunnel junction memory cell), electrons migrate between the data layer and the reference layer through the intermediate layer. The intermediate layer is typically a thin dielectric layer commonly referred to as a tunnel barrier layer. The phenomena that cause the migration of electrons through the barrier layer may be referred to as quantum mechanical tunneling or spin tunneling. The logic state may be determined by measuring the resistance of the memory cell. For example, if the overall orientation of the magnetization in the data storage layer is parallel to the pinned orientation of magnetization in the reference layer the magnetic memory cell will be in a state of low resistance. If the overall orientation of the magnetization in the data storage layer is anti-parallel (opposite) to the pinned orientation of magnetization in the reference layer the magnetic memory cell will be in a state of high resistance.
In an ideal setting the orientation of the alterable magnetic field in the data layer would be either parallel or anti-parallel with respect to the field of the reference layer. As both the data layer and the reference layer are generally both made from ferromagnetic materials and are positioned in close permanent proximity to each other, the generally stronger reference layer may affect the orientation of the data layer. More specifically, the magnetization of the reference layer may generate a demagnetization field that extends sufficiently from the reference layer into the data layer.
The result of this demagnetization field from the reference layer is an offset in the coercive switching field. This offset can result in an asymmetry in the switching characteristics of the bit: the amount of switching field needed to switch the bit from parallel to anti-parallel state is different from the switching field needed to switch the bit from anti-parallel state to parallel state. To have reliable switching characteristics and to simplify the read/write circuitry, it is desirable to have this offset reduced to as near zero as possible.
The magnetoresistance ΔR/R may be described as akin to a signal-to-noise ratio S/N. A higher S/N results in a stronger signal that can be sensed to determine the state of the bit in the data layer. Thus, at least one disadvantage of a tunnel junction memory cell having a pinned reference layer in close and fixed proximity to the data layer is a potential reduction in the magnetoresistance ΔR/R resulting from the angular displacement.
To pin the reference layer during manufacturing, the reference layer must be heated to an elevated temperature in an annealing step. The annealing step typically takes time, perhaps an hour or more. As the reference layer is but one part of the memory being produced, the entire memory must be subject to temperatures ranging from about 200 to 300 degrees centigrade while under the influence of a constant and focused magnetic field. Such manufacturing stresses may permit the reference layer to become un-pinned and lose it's set orientation if the memory is later subjected to high temperatures. In addition, the characteristics of the data layer may be unknowingly affected by the annealing heat during some manufacturing processes.
To facilitate establishing a pinned reference layer it is not uncommon for the reference layer to include multiple layers of material. While utilizing multiple layers may help insure that the reference layer remains pinned, it also raises the complexity of manufacturing each and every memory cell present in the magnetic memory.
As computer manufacturers and code developers strive to achieve faster and more powerful systems and applications, the speed of access and total memory capacity of mass storage devices become focal points of concern. Advances in technology have greatly increased the storage capacity of mass storage devices such as hard drives. However generally speaking mass storage devices employ a system of physical movement to read and write data over high cost electronic access methods utilized in traditional main memory.
The physical movement component of a mass storage device directly affects the latency in accessing data. For example, the latency in access time with hard drives is a factor of: 1) moving the read head to the appropriate radial location over the spinning disk, and 2) waiting for the spinning disk to rotate sufficiently to place the desired data bit directly in line with the read head.
Because hard disks may rotate at several thousand revolutions per minute, precise tolerances in manufacturing must be maintained to ensure that read/write transport does not inadvertently contact the media storage surface and cause damage. In addition, the data bits provided upon the disk must be placed sufficiently apart from one another such that the magnetic read/write fields applied to one data bit do not inadvertently alter neighboring data bits. This issue of providing buffering space between magnetic data bits is common in many forms of magnetic storage as used in both main and mass storage devices.
The developer of the present invention, Hewlett-Packard, Inc., has been researching ultra-high-density mass storage devices with storage areas sized on the nanometer scale. One particular field of such nanometer mass storage devices is probe based storage. In such a system a physical probe is moved from one memory location to another to read/write data to a particular location.
With respect to magnetic memory components, it is well known that as size decreases coercivity increases. A large coercivity is generally undesirable as it requires a greater electrical field to be switched, which in turn requires a greater power source and potentially larger conductor. Providing large power sources and large conductors is generally at odds with the focus of nanotechnology to reduce the necessary size of components. In addition, to mitigate the potential of inadvertently switching a neighboring memory cell, nanometer scaled memory cells are generally more widely spaced relative to their overall size than are non-nanometer sized memory cells. Moreover, as the size of the magnetic memory decreases, the unused space between individual memory cells tends to increase.
Hence, in a nanotip magnetic memory array a significant amount of overall space may be used simply to provide a physical buffer between the cells. Absent this buffering space, or otherwise reducing it's ratio, a greater volume of storage in the same physical space could be obtained. In addition, the large currents and potentially large conductors impose physical stresses upon the design and implementation of nanotip probes.
Hence, there is a need for an ultra-high density nanotip memory array which overcomes one or more of the drawbacks identified above. The present invention satisfies one or more of these needs.